This disclosure relates to integrated circuit devices, and more specifically, to an advanced method and structure to create multiple gate width patterning in semiconductor devices.
As the dimensions of modern integrated circuitry in semiconductor chips continues to become smaller, conventional lithography is increasingly challenged to make smaller and smaller structures. Sidewall Image Transfer (SIT) patterning for forming a gate structure is frequently used for gate pitches below 64 nm. However, multiple gate width patterning at such small pitches becomes complicated at hard mask assembly. It often requires complicated, multiple mask layers and complex patterning schemes. Further, the prior art process is susceptible to pitch walk for the gate structures without careful process control.
The present disclosure presents an advanced sidewall image transfer process for multiple gate width patterning to alleviate this problem.